The present invention relates to a method of logically simulating a data processing apparatus and a system for carrying out the method.
A technique for logical simulation of a data or information processing apparatus has heretofore been known, as is disclosed in Japanese Patent Application Laid-Open No. 148971/1984 (JP-A-59-148971). The working principle of this known logical simulation is illustrated in FIG. 2, while the relevant system structure is shown in FIG. 3.
In the first place, the working principle of the prior art logical simulation technique will be described by referring to FIG. 2.
A test program (hereinafter referred to as TMP in abbreviation) for a data processing apparatus is basically composed of three portions or sections, i.e. an initializing section for preparing initial data required for performing the test, a test executing section for executing the test, a result deciding section for checking and deciding the results of the test.
The TMP is loaded in a storage (hereinafter also referred to as RAM-related pseudo-procedure) which can be accessed from a logic circuit under test (hereinafter also referred to as the logic circuit model), wherein the logic circuit under test is activated by simulation data to thereby perform the logic simulation by executing the TMP placed in the storage or the RAM-related pseudo-procedure.
In conjunction with the execution of the logical simulation of a data processing apparatus, it is noted that when the TMP is executed straightforwardly as the input data for performing the logical simulation, the initializing section and the result judging or deciding section for which the logical simulation is inherently unnecessary will be executed, so that it takes enormous computer operation time because the speed at which instructions for logical simulation are executed is generally lower than the speed of executing the real machine instruction by a factor of 10.sup.8 to 10.sup.9. The initializing section and the result deciding section of the TMP are inherently destined for performing preprocessing and post-processing for logical recognition and confirmation of the test aimed by the TMP, and a string of instructions to be executed by these sections have been previously logically confirmed by means of other TMP. The number of instruction steps to be executed in the initializing section and the result deciding section is generally on the order of several times to several thousand times as large as the number of the instruction steps to be executed in the test executing section of the TMP. However, since the computer running time is imposed with limitation, it is impossible to execute the TMP for the logical simulation to the last bit of the TMP, when it is of a large scale.
Such being the circumstance, in the case of the aforementioned known data processing apparatus, a logic function model is connected to the logical simulation system in such an arrangement in which instead of logically simulating each of the logic circuits one by one, the instructions of the TMP are executed at a high speed at the functional level by describing and executing the functional operation procedures of the instructions so that the results of execution of the instructions can be made available at an increased speed. To this end, the initializing section and the result deciding section of the TMP are executed with the aid of the logic function model, while only the test executing section is executed by a logic circuit model which is a logic design array composed of basic logic elements which are capable of calculating operation process in detail, with a view to accomplishing the execution of the TMP more effectively. In general, the speed at which instruction is executed by the logic function model is higher than the instruction executing speed of the logic circuit model by a factor of 10.sup.3 to 10.sup.4.
In FIG. 2, a reference numeral 10 denotes a group of logic units of a logic circuit model, and 11 denotes a group of operational functions of a logic function model. In those groups, a symbol IU represents an instruction control unit, BU represents a buffer control unit, FU represents a floating point arithmetic operation unit, GU represents a general-purpose arithmetic operation unit, SU represents a storage control unit, and CU represents a common control unit.
Referring to FIG. 2, the TMP is executed in the manner mentioned below. At first, instructions of the initialize section are executed by the logic function model at a high speed. When an operation mode change-over instruction is detected upon completed execution of the instructions of the initialize section, the instruction executing model is changed over from the logic function model to the logic circuit model. For the purpose of changing over the operative model between the logic function model and the logic circuit model, two types of instructions are newly prepared for realizing the switching from the former to the latter and vice versa. When a given model detects the instruction commanding the switching from one to the other model, execution of the current instruction by the given model is interrupted, being followed by activation of the other model through a communication routine. Subsequently, the instructions belonging to the test executing section are executed in the logic circuit model. When the operative model switch instruction is detected upon completed execution of the instructions belonging to the test executing section by the logic circuit model, the instruction executing model is reversely switched from the logic circuit model to the logic function model. With the logic function model, the instructions belonging to the result decision section are executed at a high speed. At the end of execution of the instructions belonging to the result deciding section, the logic function model starts to execute the instructions belonging to the initialize section of a succeeding test. Subsequently, the process mentioned above is repeated for executing sequentially the individual testing sections of the TMP.
Next, the system structure and operations of the prior art logical simulation technique will be described in detail by referring to FIG. 3.
The logic circuit model 12 is composed of a group of logic units 15 composed of basic logic elements capable of calculating operation processes in detail such as IU (instruction control unit), BU (buffer control unit), FU (floating point operation unit), GU (general-purpose operation unit), SU (storage control unit), CU (common control unit) and the like which cooperate to constitute a data processing system to be tested, and a register(REG)-related pseudo-procedure 16 (hereinafter referred to as REG-related pseudo-procedure in abbreviation) which includes CPU status words 161 (hereinafter referred to as PSW in abbreviation) dispersed among the aforementioned individual units, a general-purpose register 162 (hereinafter referred to as GR in abbreviation), a control register 163 (hereinafter referred to as CR in abbreviation) and the like.
The logic function model 13 is, so to say, a sort of pseudo-procedure describing the functional operations of an ordinary data processing apparatus (which may be the one to be tested) in terms of machine word instructions and includes internally an operational function group of the IU, BU, FU, GU, SU, CU and other units, and internal registers 18 including the PSW 181, GR 182, CR 183 and others in correspondence with the aforemetioned logic circuit model. The communication routine 14 is described in terms of logical simulation language and machine word instructions for performing the control of execution of the instructions and data transfer between the logic circuit model 12 and the logic function model 13. The memory-related pseudo-procedure 8 (hereinafter referred to as RAM-related pseudo-procedure) defines memory chips with the function of the logical simulation for a variety of memories incorporated in the data processing apparatus under test and describes the access operations to the memory chips in terms of the logical simulation language and a common program language. Both the logic circuit model 12 and the logic function model 13 can make access in common to the RAM-related pseudo-procedure 8.
Now, exemplary logical simulation operation realized by the hitherto known system of the structure described above will be discussed below in detail.
At first, the communication routine 14 performs the processings for starting the logical simulation (SIM) such as initialization, resetting of the logic circuit model 12, generation of clock signal, loading of initial values in the various registers such as PSW 161, GR 162, CR 163 and others. Subsequently, the communication routine 14 activates the processing of the logic function model 13 by utilizing various information inclusive of data placed in the various registers such as PSW 161, GR 162, CR 163 and others. For executing the instructions belonging to the initialize section, the logic function model 13 loads the internal register 18 with the information of the PSW 161, GR 162, CR 163 and others included in the REG-related pseudo-procedure 16 and received by way of the communication routine 14. Subsequently, the logic function model 13 reads out the instruction designated by the PSW 181 in the internal register 18 from the RAM-related pseudo-procedure 8 (e.g. a main storage or MS 81).
When the decoding of the instruction read out has proved that the operands designate the register, the operands as required are read out from the internal register 18 incorporated in the logic function model 13. On the other hand, when operands designate the memory, the requisite operands are read out from the RAM-related pseudo-procedure 8. On the basis of the operands as read out, a predetermined operation is conducted, the result of which is loaded in the internal register 18 of the logic function model 13 when the operands designate the register as the destined storage therefor, while the result of the operation is written in the RAM-related pseudo-procedure 8 when the memory is designated as the destined storage. When execution of the instruction has been completed, the instruction address of the PSW 181 is updated to allow a succeeding instruction to be read out, which instruction is then executed in the similar manner described above. This operation is repeatedly performed for all the instructions contained in the initialize section of the TMP.
Upon completed execution of the instruction of the initialize section, the logic function model 13 interrupts the instruction executing operation and sends the updated contents of the various registers PSW 181, GR 182 and CR 183 as well as other various information to the communication routine 14. On the basis of the information as received, the communication routine 14 makes a decision as to whether or not continuation of the logical simulation is still necessary. If unnecessary, the logical simulation ending processing, such as the displaying of the resulted codes, is performed. On the other hand, when it is decided that the logical simulation is to be continued, the values or data of the PSW 181, GR 182, CR 183 and other registers sent from the logic function model 13 are placed in the REG-related pseudo-procedure 16 included in the logic circuit model 12 which is then activated. For executing the test executing section of the TMP, the logic circuit model 12 refers to the information placed in the PSW through the medium of the communication routine 14 to read out the designated instruction from the RAM-related pseudo-procedure 8. The instruction is decoded. When the operands resulting from the decoding designate the register, the requisite operands are read out from the REG-related pseudo-procedure 16. When the operands designate the memory, the requisite operands are read out from the RAM-related pseudo-procedure 8. With the operands as read out, a predetermined operation is performed. For storage of the result of operation, it is set in the REG-related pseudo-procedure 16 when the operands designate the register as the destined storage thereof, while the result of operation is written in the RAM-related pseudo-procedure 8 when the operands designate the memory. At the end of execution of the instruction, the instruction address of the PSW 161 is updated to allow a succeeding instruction to be read out. The instruction thus read out is executed in a similar manner as described above. This operation is repeatedly performed for all the instructions of the test executing section of the TMP.
When the execution of the instructions contained in the test executing section has been completed, the logic circuit model 12 interrupts the instruction executing operation and sends the updated data placed in the PSW 161, GR 162, CR 163 and other registers together with various data to the communication routine 14. The latter then activates the logic function model 13 with the updated data of the PSW 161, GR 162, CR 163 and other registers together with various information required for the activation. The logic function model 13 places in the internal register 18 the data received from the PSW 161, GR 162, CR 163 and other registers by way of the communication routine 14 for executing instructions included in the result decide section of the TMP. Subsequently, the logic function model 13 reads out the instruction designated by the PSW 181 from the RAM-related pseudo-procedure 8.
Subsequently, execution of the instruction is repeated in the similar manner as the execution of the instruction for the initialize section to complete execution of all the instructions of the result decide section.
When it is found upon completion of execution of the instructions for the result decision section that another test is to be consecutively performed with the TMP, the logic function model 13 executes the initialize section for the next test in the similar manner as described above. Upon completed execution of the instructions of the initialize section for the next test or at the end of the completed execution of the whole TMP, the logic function model 13 interrupts or stops the instruction executing operation and sends to the communication routine 14 the updated data of the PSW 181, GR 182, CR 183 and other registers together with various information.
On the basis of the data and information received from the logic function model 13, the communication routine 14 makes decision as to the necessity of continuation of the logical simulation. When the simulation is found to be continued, the logic circuit model 12 is again activated through the same procedure as described above to repeat the execution of instructions. On the other hand, if it is decided that continuation of the simulation is unnecessary, the logical simulation ending processing such as the displaying of the resulting codes and the like is performed, whereupon the logic simulation procedure comes to an end.
The prior art technique described above suffers a problem mentioned below. Namely, even when the logic circuit model is developed precedingly for a given one unit (e.g. general-purpose operation unit or GU) among a plurality of the logic units which constitute one instruction of the data processing system to be tested, the logical verification of the preceding unit can not be performed through the logical simulation by using the TMP, unless the instruction control unit (IU) for decoding the instruction, the memory control unit (SU) for reading out the operands required for the operation from the memory in response to the request from the IU, the buffer control unit (BU) and the like are available.
Another problem of the prior art system can be seen in the fact that since the logical verification for only a part of the units requires all the other units to be connected, the expected results can not be obtained by performing the logical simulation when any one of the other units suffers logical errors.
Besides, in case the logic circuit model is of a large scale, all the individual AND circuits, OR circuits and the like which constitute the logic circuit model have to be exploded on the computer memory before performing the logical simulation, the capacity of the computer memory used for the logical simulation as well as the time taken for the computer to run is significantly increased, involving extended turn-around time for the job output.